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| 4-bit single chip microcomputers gms34xxxt series user`s manual ? gms34004t ? gms34112t ? GMS34140T
revision 1.0 published by mcu application team in hyundai electronics industrial co., ltd. " " hyundai electronics industrial co., ltd. 1996 all right reserved. editor's e-mail : kanghan@hei.co.kr lbkd@hei.co.kr rhja@hei.co.kr additional information of this manual may be served by hyundai electronics industrial offices in korea or distributors and representative listed at address directory. hyundai electronics industrial reserves the right to make changes to any information here in at any time without notice. the information, diagrams, and other data in this manual are correct and reliable; however, hyundai electronics industrial co., ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. table of contents chapter 1 introduction outline of characteristics characteristics block diagram pin assignment and terminal pin dimension pin description and circuit i/o circuit types and options electrical characteristics chapter 2 architecture block description program memory (rom) eprom address register data memory (ram) x-register (x) y-register (y) accumulator (acc) arithmetic and logic unit (alu) state counter (sc) clock generator pulse generator initial reset circuit watch dog timer (wdt) stop function port operation chapter 3 instruction table of contents ............................................................................................1-1 .................................................................1-1 ..................................................................................1-1 ..................................................................................1-2 ..........................................................1-3 ..................................................................................1-4 .................................................................1-7 .............................................................1-8 ................................................................1-10 ...........................................................................................2-1 .............................................................................2-1 ..................................................................2-1 ................................................................2-2 ........................................................................2-3 ...................................................................................2-3 ...................................................................................2-4 ............................................................................2-4 .......................................................2-4 ...........................................................................2-5 ...............................................................................2-6 ...............................................................................2-7 ............................................................................2-8 .................................................................2-8 ....................................................................................2-9 ..................................................................................2-9 ........................................................................................3-1 table of contents chapter 4 eprom gms34004tk/34112tk/34140tk mode define port define programming data write/read data conversion checksum programming control programming dc specification eprom read mode(1/2) eprom read mode (2/2) eprom write mode (1/2) eprom write mode (2/2) lock bit write mode (1/2) lock bit write mode (2/2) lock bit read mode (1/2) lock bit read mode (2/2) gms34004t/112t/140t (pin assignment & package) eprom (khz) mode eprom write only mode gms34004tk/34112tk/34140tk mode define port define programming data write/read data conversion checksum programming control programming dc specification eprom read mode(1/2) eprom read mode (2/2) eprom write mode (1/4) eprom write mode (2/4) eprom write mode (3/4) eprom write mode (4/4) lock bit write mode (1/3) lock bit write mode (2/3) lock bit write mode (3/3) lock bit read mode (1/2) lock bit read mode (2/2) .................................................................................................4-1 .........................................................4-1 .....................................................................................4-1 .......................................................................................4-2 ...........................................................................4-2 ............................................................4-3 .........................................................................................4-3 ........................................................................4-3 .........................................................4-3 ...................................................................4-4 ..................................................................4-4 ..................................................................4-5 ..................................................................4-5 ..................................................................4-6 ..................................................................4-6 ..................................................................4-7 ..................................................................4-7 .....................4-8 .........................................................................4-9 ..................................................................4-9 .............................................................4-10 .....................................................................................4-10 ........................................................................................4-11 ...........................................................................4-11 ............................................................4-12 ........................................................................................4-12 ......................................................................4-12 ........................................................4-12 ...................................................................4-13 ...................................................................4-13 ..................................................................4-14 ..................................................................4-14 ..................................................................4-15 ..................................................................4-15 ..................................................................4-16 ..................................................................4-16 ..................................................................4-16 ..................................................................4-18 ..................................................................4-18 introduction 1 architecture 2 instruction 3 eprom 4 1 - 1 chapter 1. introduction outline of characteristics the gms340 series are remote control transmitter which uses cmos technology, and the eprom version of gms34xxx series. this enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. the gms340 series are suitable for remote control of tv, vcr, fans, air- conditioners, audio equipments, toys, games etc. characteristics program memory : 512bytes for gms34004t 1,024 bytes for gms34112t/140t data memory : 32 ?? 4 bits 43 types of instruction set 3 levels of subroutine nesting 1 bit output port for a large current (remout signal) operating frequency : 300khz~500khz at khz version 2.4mhz~4mhz at mhz version 300khz~4.2mhz at wide version instruction cycle : f osc /6 at khz and wide version f osc /48 at mhz version cmos process (3.0v or 5.0v power supply) stop mode (through internal instruction) released stop mode by key input built in capacitor for ceramic oscillation circuit at khz version built in a watch dog timer (wdt) low operating voltage : 2.2~4.5v (at khz and mhz version) normal operating voltage : 4.0~5.0v (at wide version) table 1-1 gms34xxxt series members chapter 1. introduction series program memory data memory i/o ports input ports output ports package khz version mhz version wide version gms34004t 512 32 ?? 4 - 4 6 d0 ~ d5 16dip gms34004tk gms34004tm gms34004tw gms34112t 1,024 ?? 4 ?? ?? ?? 20dip/sop/ssop gms34112tk gms34112tm gms34112tw GMS34140T ?? ?? ?? ?? 10 d0 ~ d9 24dip/sop GMS34140Tk GMS34140Tm GMS34140Tw 1 - 2 block diagram fig 1-1 block diagram (in case of GMS34140T) chapter 1. introduction ram 16word x 2page x 4bit ram word selector y-reg acc st r-latch d-latch pulse generator x-reg mux mux alu 23 22 7 8 9 4 21 10 3 5 6 11 12 13 14 15 16 17 18 19 20 instruction decoder program counter stack reset watchdog timer 1 24 2 10 10 8 rom 64word ?? 16page ?? 8bit 8 4 4 2 4 10 4 10 4 4 4 16 4 4 4 4 4 osc1 osc2 k0 ~ k3 r0 ~ r3 d0 ~ d9 remout reset/vpp vdd gnd osc control signal 1 - 3 pin assignment and terminals pin assignment fig 1-2 gms34004t pin assignment (16pdip) fig 1-3 gms34112t pin assignment (20dip/sop) fig 1-4 gms34112t pin assignment (20ssop only) chapter 1. introduction fig 1-5 GMS34140T pin assignment (24dip/sop) vdd osc1 osc2 remout d5 d4 d3 d2 reset/vpp gnd k0 k1 k2 k3 d0 d1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r3 r2 r1 r0 gnd reset/vpp vdd osc1 osc2 remout k0 k1 k2 k3 d0 d1 d2 d3 d4 d5 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 reset/vpp vdd osc1 osc2 remout d5 d4 d3 d2 d1 gnd r0 r1 r2 r3 k0 k1 k2 k3 d0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 reset/vpp gnd r0 r1 r2 r3 k0 k1 k2 k3 d0 d8 vdd osc1 osc2 remout d7 d6 d5 d4 d3 d2 d1 d9 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 14 13 1 - 4 pin dimension fig 1-6 16pdip pin dimension 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0.785max 0.745min 0.040max 0.020min 0.065max 0.015min 0.140max 0.120min ?? ?? ?? ?? 0~15 ?? 0.260max 0.240min 0.300bsc 0.014max 0.008min outline (unit:inch) 0.050min 0.022max 0.015min 0.100bsc 0.125min 0.135max 0.170max 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 0.984max 0.968min 0.065max 0.055min 0.022max 0.015min 0.1typ 0.170max 0.015min 0.135max 0.125min ?? ?? ?? ?? 0~15 ?? 0.270max 0.250min 0.3typ 0.012max 0.008min outline (unit : inch) fig 1-7 20pdip pin dimension chapter 1. introduction 1 - 5 0.5118max 0.4961min 0.020max 0.014min 0.05typ 0.0118max 0.004min 1 2 3 4 5 6 7 8 9 10 20 19 1 8 17 16 15 14 13 12 11 ?? ?? ?? ?? 0.299max 0.292min 0.419max 0.0125max 0.0091min 0.104max 0.093min 0.042max 0.016min outline (unit : inch) 0.398min fig 1-8 20sop pin dimension chapter 1. introduction 0.344max 0.337min 0.012max 0.008min 0.025bsc 1 2 3 4 5 6 7 8 9 10 20 19 1 8 17 16 15 14 13 12 11 ?? ?? ?? ?? 0.010max 0.007min 0.032max 0.022min outline (unit : inch) fig 1-9 20ssop pin dimension 0.244max 0.234min 0.157max 0.150min 0.066max 0.057min 0.010max 0.004min 0-8 a ? ? 1 - 6 chapter 1. introduction fig 1-11 24sop pin dimension 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1.255max 1.245min 0.065max 0.055min 0.022max 0.015min 0.1typ 0.015min 0.135max 0.125min ?? ?? ?? ?? 0~15 a 0.270max 0.250min 0.3typ 0.012max 0.008min outline (unit : inch) fig 1-10 24skinny dip pin dimension 0.170max 0.616max 0.595min 0.020max 0.014min 0.05typ 0.018max 0.004min 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ?? ?? ?? ?? 0.299max 0.292min 0.419max 0.398min 0.0125max 0.0091min 0.042max 0.016min outline (unit : inch) 0.104max 0.093min 1 - 7 pin function pin description and circuit pin description i/o connected to 2.2~4.5v power supply at khz and mhz version or 4.0 ~ 5.5v power supply at wide version. connected to 0v power supply. used to input a manual reset. when the pin goes "l", the d-output ports and remout-output port are initialized to "l", and rom address is set to address 0 on page 0. for programming, this pin receives 12.5v programming voltage. 4-bit input port. stop mode is released by "l" input of each pin. the output is the structure of n-channel-open-drain. 4-bit i/o port. (input mode is set only when each of them output "h".) in outputting, each can be set and reset independently(or at once.) the output is in the form of c-mos. stop mode is released by "l" input of each pin. high current output port. the output is in the form of c-mos. the state of large current on is "h". oscillator input. input to the oscillator circuit and connection point for ceramic resonator. internal capacitors available at khz version. a feedback resistor is connected between this pin and osc2. connect a resonator between this pin and osc1. v dd gnd reset k0~k3 d0~d9 r0~r3 remout osc1 osc2 input input output i/o output input output - - chapter 1. introduction 1 - 8 i/o circuit types and options hysteresis input type. built in pull-up-resistor, typical 800 ? reset/vpp i pin i/o note ?? ?? ?? ?? cmos output. "h" output at reset. built in mos tr for pull-up about 120 ? . r0~r3 i/o built in mos tr for pull-up about 120 ? . k0~k3 i open drain output. "l" output at reset. d0~d9 o ?? ?? cmos output. "l" output at reset. high current output source. remout o i/o circuit ?? ?? ?? ?? ?? ?? ?? ?? pull-up chapter 1. introduction pull-up 1 - 9 built in feedback-resistor about 1 ? osc2 o pin i/o note built in resonance capacitor at khz version c1=c2 = 100pf ?? 15% [c1,c2 are not available for mhz and wide version] osc1 i i/o circuit built in damping-resistor rd = 4 ? [no resistor in mhz operation] ?? ?? ?? ?? ? ? osc2 rd c2 rf c1 osc1 stop chapter 1. introduction frequency resonator maker part name load capacitor 320khz cq ztb320d c1=c2=open ztb500e c1=c2=open 500khz cq 3.43mhz cq zta3.43mg c1=c2=30pf tdk fcr3.52m5 c1=c2=33pf cq zta3.64mg c1=c2=30pf 3.84mhz tdk fcr3.64m5 c1=c2=33pf cq zta3.84mg c1=c2=30pf tdk fcr3.84m5 c1=c2=33pf cq recommend 430khz~500khz resonator 3.52mhz 3.64mhz 4.00mhz cq zta4.00mg c1=c2=30pf 1 - 10 parameter supply voltage programming voltage power dissipation storage temperature range input voltage output voltage unit v v mw ? v v electrical characteristics absolute maximum ratings (ta = 25 ? ) symbol v dd v pp p d tstg v in v out max. rating -0.3 ~ 7.0 -0.3 ~ 13.5 700 * -55 ~ 125 -0.3 ~ v dd +0.3 -0.3 ~ v dd +0.3 * thermal derating above 25 ? : 6mw per degree ? rise in temperature. parameter supply voltage operating temperature unit v ? recommended operation condition rating 2.2 ~ 4.5 2.2 ~ 4.5 4.0 ~ 5.5 -20 ~ +70 chapter 1. introduction condition 300 ~ 500khz 2.4 ~ 4mhz 300khz ~ 4.2mhz - symbol v dd topr 1 - 11 electrical characteristics for low voltage products (ta=25 ? , v dd =3v) chapter 1. introduction parameter symbol limits unit condition f osc /6 f osc /48 f osc input h current reset input l current k, r input l current k, r input h voltage reset input h voltage reset input l voltage d. r output l voltage remout output l voltage remout output h voltage osc2 output l voltage osc2 output h voltage d, r output leakage current current on stop mode operating supply current 1 operating supply current 2 system clock frequency k, r input l voltage f osc i dd2 * i dd1 * i stop i ol v oh3 v ol3 v oh1 v ol2 v il2 v ih2 v il1 v ih1 i il1 i il2 i ih v ol1 2.4 300 - - - - 2.1 - 2.1 - - 2.25 - 2.1 -9 -2 - - - - 0.5 0.3 - - 2.5 0.4 2.5 0.15 - - - - -25 -7.5 - 0.15 min. typ. max. 4 500 4.0 4.0 1 1 - 0.9 - 0.4 0.75 - 0.9 - -50 -16 1 0.4 mhz khz ma ma ua ua v v v v v v v v ua ua ua v f osc =4mhz f osc =455khz at stop mode v 0ut =v dd , output off i oh =70ua i ol =70ua i oh =-8ma i ol =1ma v - - - vi=gnd, output off, pull-up resistor provided. vi=gnd vi=v dd i ol =100ua khz version mhz version * i dd1 , i dd2 , is measured at reset mode. 1 - 12 parameter electrical characteristics (ta=25 ? , v dd =5v) symb ol limits unit condition f osc /6 input h current reset input l current k, r input l current k, r input h voltage reset input h voltage reset input l voltage d. r output l voltage remout output l voltage remout output h voltage osc2 output l voltage osc2 output h voltage d, r output leakage current current on stop mode operating supply current system clock frequency k, r input l voltage f osc i dd i stop i ol v oh3 v ol3 v oh1 v ol2 v il2 v ih2 v il1 v ih1 i il1 i il2 i ih v ol1 0.3 - - - v dd -1.0 - v dd -1.0 - - 0.75*v dd - 0.7*v dd -9 -2 - - - - - - - - - - - - - - - - - - min. typ. max. 4.2 10 10 5 - 0.9 - 0.4 0.25*v dd - 0.3*v dd - -150 -20 5 0.4 mhz ma ua ua v v v v v v v v ua ua ua v at reset mode at stop mode v 0ut =v dd , output off i oh =-70ua i ol =70ua i oh =-8ma i ol =2ma v - - - vi=gnd, output off, pull-up resistor provided. vi=gnd vi=v dd i ol =100ua wide version chapter 1. introduction introduction 1 architecture 2 instruction 3 eprom 4 2 - 1 chapter 2. architecture block description program memory (eprom) the gms34xxxt series can incorporate maximum 1,024 words (64 words ?? 16 pages ?? 8bits) for program memory. program counter pc (a0~a5) and page address register (a6~a9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. the program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. the program memory is composed as shown below. 0 1 2 3 4 5 6 7 8 63 program counter (pc) page address register (pa) page buffer (pb) 6 4 (level "1") (level "2") (level "3") (psr) (sr) stack register page 0 page 1 page 2 page 15 a0~a5 0 1 2 15 a6~a9 program capacity (pages) fig 2-1 configuration of program memory chapter 2. architecture 4 2 - 2 eprom address register the following registers are used to address the eprom. ? page address register (pa) : holds eprom's page number (0~fh) to be addressed. ? page buffer register (pb) : value of pb is loaded by an lpbi command when newly addressing a page. then it is shifted into the pa when rightly executing a branch instruction (br) and a subroutine call (cal). ? program counter (pc) : available for addressing word on each page. ? stack register (sr) : stores returned-word address in the subroutine call mode. (1) page address register and page buffer register : address one of pages #0 to #15 in the eprom by the 4-bit binary counter. unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. to change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of lpbi) and (2) execution of br or cal, because instruction code is of eight bits so that page and word can not be specified at the same time. in case a return instruction (rtn) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) program counter : this 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. for easier programming, at turning on the power, the program counter is reset to the zero location. the pa is also set to "0". then the program counter specifies the next eprom address in random sequence. when br, cal or rtn instructions are decoded, the switches on each step are turned off not to update the address. then, for br or cal, address data are taken in from the instruction operands (a 0 to a 5 ), or for rtn, and address is fetched from stack register no. 1. (3) stack register : this stack register provides two stages each for the program counter (6 bits) and the page address register (4bits) so that subroutine nesting can be made on two levels. chapter 2. architecture 2 - 3 data memory (ram) up to 32 nibbles (16 words ?? 2pages ?? 4bits) is incorporated for storing data. the whole data memory area is indirectly specified by a data pointer (x,y). page number is specified by zero bit of x register, and words in the page by 4 bits in y-register. data memory is composed in 16 nibbles/page. figure 2-2 shows the configuration. 0 1 2 3 15 output port y-register (y) x-register (x) d0 d9 r0 r3 remout page 0 page 1 0 1 4 a0~a3 data memory page (0~1) x-register (x) x-register is consist of 2bit, x0 is a data pointer of page in the ram, x1 is only used for selecting of d8~d9 with value of y-register fig 2-2 composition of data memory x1=1 x1=0 d8 d9 y=0 y=1 d1 d0 table 2-1 mapping table between x and y register chapter 2. architecture 4 2 2 - 4 y-register (y) y-register has 4 bits. it operates as a data pointer or a general-purpose register. y-register specifies and address (a 0 ~a 3 ) in a page of data memory, as well as it is used to specify an output port. further it is used to specify a mode of carrier signal outputted from the remout port. it can also be treated as a general- purpose register on a program. accumulator (a cc ) the 4-bit register for holding data and calculation results. arithmetic and logic unit (alu) in this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) operation circuit (alu) : the adder/comparator serves fundamentally for full addition and data comparison. it executes subtraction by making a complement by processing an inversed output of a cc (a cc +1) (2) status logic : this is to bring an st, or flag to control the flow of a program. it occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. chapter 2. architecture 2 - 5 state counter (sc) a fundamental machine cycle timing chart is shown below. every instruction is one byte length. its execution time is the same. execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). exceptionally br, cal and rtn instructions is normal execution time since they change an addressing sequentially. therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. t1 t2 t3 t4 t5 t6 t1 t2 t3 t4 t5 t6 fetch cycle n execute cycle n-1 execute cycle n fetch cycle n-1 machine cycle machine cycle phase phase phase 2 fig. 2-3 fundamental timing chart chapter 2. architecture 2 - 6 clock generator the gms34xxxt series has an internal clock oscillator. the oscillator circuit is designed to operate with an external ceramic resonator. internal capacitors are available at khz version. oscillator circuit is able to organize by connecting ceramic resonator to outside. * it is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturer`s resonator matching guide. osc1 osc2 c1 c2 2 - 7 pulse generator the following frequency and duty ratio are selected for carrier signal outputted from the remout port depending on a pmr (pulse mode register) value set in a program. t t1 remout signal t=1/f pul = 12/f osc [96/f osc ], t1/t = 1/2 0 1 pmr 2 3 4 5 t=1/f pul = 12/f osc [96/f osc ], t1/t = 1/3 t=1/f pul = 8/f osc [64/f osc ], t1/t = 1/2 t=1/f pul = 8/f osc [64/f osc ], t1/t = 1/4 t=1/f pul = 11/f osc [88/f osc ], t1/t = 4/11 no pulse (same to d0~d9) * default value is "0" * [ ] means the value of "t", when instruction cycle is f osc /48 in mhz version table 2-2 pmr selection table 6 t=1/f pul = 12/f osc [96/f osc ], t1/t = 1/4 chapter 2. architecture 7 no pulse (same to d0 ~ d9) 2 - 8 initial reset circuit reset pin must be down to "l" more than 4 machine cycle by outside capacitor or other for power on reset. the mean of 1 machine cycle is 6/f osc or 48/f osc , however, operating voltage must be in recommended operating conditions, and clock oscillating stability. * it is required to adjust c value depending on rising time of power supply. (example shows the case of rising time shorter than 10ms.) 1 reset 0.1uf chapter 2. architecture watch dog timer (wdt) watch dog timer is organized binary of 14 steps. the signal of f osc /6 cycle comes in the first step of wdt after wdt reset. if this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. the overflow time is 6 ?? 2 13 /f osc (108.026ms at f osc =455khz.) 8 ?? 6 ?? 2 13 /f osc (108.026ms at f osc = 3.64mhz) normally, the binary counter must be reset before the overflow by using reset instruction (wdtr) or / and remout port high(y-reg=8, so instruction execution). * it is constantly reset in stop mode. when stop is released, counting is restarted. (refer to 2-9 stop function>) binary counter (14 steps) reset (edge-trigger) f osc /6 or f osc /48 cpu reset reset by instruction remout output 2 - 9 stop operation stop mode can be achieved by stop instructions. in stop mode : 1. oscillator is stopped, the operating current is low. 2. watch dog timer is reset, d8~d9 output and remout output are "l". 3. part other than wdt, d8~d9 output and remout output have a value before come into stop mode. stop mode is released when one of k or r input is going to "l". 1. state of d0~d7 output and remout output is return to state of before stop mode is achieved. 2. after 1,024 ?? 8 enable clocks for stable oscillating, first instruction start to operate. 3. in return to normal operation, wdt is counted from zero again. but, at executing stop instruction, if one of k or r input is chosen to "l", stop instruction is same to nop instruction. port operation value of x-reg value of x-reg 0 or 1 0 ~ 7 s0 : d(y) ?? 1, r0 : d(y) ?? 0 operation 0 or 1 8 remout port repeats "h" and "l" in pulse frequency. (when pmr = 5, it is fixed at "h") s0 : remout(pmr) ?? 1 r0 : remout(pmr) ?? 0 0 or 1 9 s0 : d0 ~ d9 ?? 1 (high-z) r0 : d0 ~ d9 ?? 0 0 or 1 a ~ d s0 : r(y-ah) ?? 1 r0 : r(y-ah) ?? 0 0 or 1 e s0 : r0 ~ r3 ?? 1 r0 : r0 ~ r3 ?? 0 0 or 1 f s0 : d0 ~ d9 ?? 1, r0 ~ r3 ?? 1 r0 : d0 ~ d9 ?? 0, r0 ~ r3 ?? 0 2 or 3 0 s0 : d(8) ?? 1 r0 : d(8) ?? 0 2 or 3 1 s0 : d(9) ?? 1 r0 : d(9) ?? 0 chapter 2. architecture introduction 1 architecture 2 instruction 3 eprom 4 3 - 1 chapter 3. instruction chapter 3. instruction instruction table the gms34xxxt series provides the following 43 basic instructions. category 1 2 3 register to register lay lya laz mnemonic a ?? y function y ?? a a ?? 0 s s s st *1 4 5 6 ram to register lma lmaiy lym m(x,y) ?? a m(x,y) ?? a, y ?? y+1 y ?? m(x,y) s s s 7 8 lam xma a ?? m(x,y) a ? m(x,y) s s 9 10 11 immediate lyi i lmiiy i lxi n y ?? i m(x,y) ?? i, y ?? y+1 x ?? n s s s 12 13 14 ram bit manipulation sem n rem n tm n m(n) ?? 1 m(n) ?? 0 test m(n) = 1 s s e 15 16 17 rom address br a cal a rtn if st = 1 then branch if st = 1 then subroutine call return from subroutine s s s 18 lpbi i pb ?? i s 19 20 21 arithmetic am sm im a ?? a + m(x,y) a ?? m(x,y) - a a ?? m(x,y) + 1 c b c 22 23 dm ia a ?? m(x,y) - 1 a ?? a + 1 b s 24 25 iy da y ?? y + 1 a ?? a - 1 c b 3 - 2 chapter 3. instruction category 26 27 28 arithmetic dy eorm nega mnemonic y ?? y - 1 function a ?? a + m (x,y) a ?? a + 1 b s z st *1 29 30 comparison alem alei i test a ?a m(x,y) test a ?a i e e 31 32 mnez ynea test m(x,y) ? 0 test y ? a n n 33 34 ynei i knez test y ? i test k ? 0 n n 35 rnez test r ? 0 n 36 37 input / output lak lar a ?? k a ?? r s s 38 39 so ro output(y) ?? 1 *2 output(y) ?? 0 *2 s s 40 41 control wdtr stop watch dog timer reset stop operation s s 42 43 lpy nop pmr ?? y no operation s s note) i = 0~f, n = 0~3, a = 6bit pc address *1 column st indicates conditions for changing status. symbols have the following meanings s : on executing an instruction, status is unconditionally set. c : status is only set when carry or borrow has occurred in operation. b : status is only set when borrow has not occurred in operation. e : status is only set when equality is found in comparison. n : status is only set when equality is not found in comparison. z : status is only set when the result is zero. *2 operation is settled by a value of y-register. introduction 1 architecture 2 instruction 3 eprom 4 4 - 1 chapter 4. eprom chapter 4. eprom gms34004tk / 34112tk / 34140tk mode define device operation exact user pgm address in, data out item user mode eprom read mode eprom program mode 1byte pgm write 2byte pgm write program verify lock bit write lock bit read address in, data in address in, data in address in, data out lock bit write(set d5 to 1) lock bit out mode setting resetb = 0 ~ 3v vcc=3v vcc=6.0v vcc=6.0v k3~0=0110 k3~0=0110 k3~0=0111 - k3~0=0100 k3~0=0101 resetb =12.5v resetb =12.5v lock bit program mode resetb =12.5v vcc=6.0v, lock bit is d5. (default : unlock) 4 - 2 port define chapter 4. eprom nmos open drain i/o in eprom mode * undefined ports in this table are n.c (no connection) port name vdd resetb osc1 k0 k1 k2 k3 user mode 3.0v reset (0, 3.0v) clock input k0(input) k1(input) k2(input) k3(input) eprom mode 6.0v vpp (0, 12.5v) clock input read / write control address / data control d0 d1 d2 d3 d4 d5 d0(output) d1(output) d2(output) d3(output) d4(output) d5(output) a0 a5 da0 da4 lock bit output gnd 0v a1 a6 da1 da5 a2 a7 da2 da6 a3 a8 da3 da7 a4 a9 - - programming data device name gms34004tk rom size 512bytes blank data (hex) ff lock bit yes device address 0000 ~ 01ff file address 0000 ~ 01ff gms34112tk 1,024bytes ff yes 0000 ~ 03ff 0000 ~ 03ff GMS34140Tk 1,024bytes ff yes 0000 ~ 03ff 0000 ~ 03ff - if lock bit is set, the eprom of the device can not be read, because output is always ff. - input file : intel hexa format ( *.rhx ) 4 - 3 chapter 4. eprom write / read data conversion - you must change msb ~ lsb ? lsb ~ msb. - example hex binary (msb~lsb) 2c e4 8d 0010 1100 1110 0100 1000 1101 write read hex binary (msb~lsb) 34 27 b1 0011 0100 0010 0111 1011 0001 file / buffer data device (d3 ~ d0) checksum - it is calculated from the buffer of the programmer. - address range is the same as device address. - calculate method is the same as normal eprom devices (ex:27c128, 256 etc) programming control - osc1 & resetb control otp device, so you must count osc1 clocks in every state. - k ports control the internal state of the otp device(ex: read, write...). - d5~d0 ports are nmos open drain i/o in eprom mode. it must be pulled up by resistors (about 4.7~ 47k ohm). - the frequency rate of the osc1 clock is 10khz ~ 500khz. you can hold osc1 high or low state when you need. item range vcc 0 ~ 6.0v ?? 0.25v programming dc specification resetb 0 ~ 12.5v ?? 0.5v k-port d-port 0 ~ 0.2vcc(low) 0.8vcc ~ vcc (high) 4 - 4 chapter 4. eprom eprom read mode (1/2) al : low address (a4~0) input latch oh : high data (d7~4) output ol : low data (d3~0) output ah : high address (a9~5) input latch for device verify or read. if you set lock bit, output data is always ff. * note : 1. ah, al, dh, dl inputs released at 100~200ns after osc rising edge and width is 1osc cycle ( if osc is 500khz, width is 2us ). resetb osc 12.5v ck1 ck2 ck3 k3 ~ k0 0110 ah d4 ~ d0 0000 vcc 6v 0v al oh ol 1101 ah al oh ol ah al oh ol ah al oh ol 0000 1101 0000 1101 0000 1101 addr. 0 addr. 1 addr. 2 addr. 3 1 2 3 2us at 500khz ? ? ? 14.5clocks eprom read mode (2/2) start end ? reset (set eprom read mode) address=first address set address read data address ++ address > last address resetb=0v vcc=0v 4 - 5 chapter 4. eprom eprom write mode (1/2) resetb osc 12.5v ck1 ck2 ck3 k3 ~ k0 pgm write ( 0110 ) ah d4 ~ d0 0000 1101 vcc 6v 0v 1000 1110 0000 1000 al dh dl ah al dh dl oh ol 10times repeat 12us x 10 = 120us verify next write ah : high bit address input latch al : low bit address input latch dh : high bit data input latch dl : low bit data input latch oh : high bit data output ol : low bit data output 9.5v 1 2 3 4 * note : 1. ah, al, dh, dl inputs are released at 100~200ns after osc rising edge and width is 1osc cycle ( if osc is 500khz, width is 2us ). 2us at 500khz ? ? ? 14.5clocks eprom write mode (2/2) no fail yes pass no fail pass yes start ? reset (set eprom write mode) address=first address set address & data eprom write repeat until near 100us. when 500khz osc1, repeat 10 times (12us*10=120us) resetb=0v vcc=0v end count=0 count ++ verify count=25? device fail address ++ eprom write (write one more time) address > last address eprom read mode verify all resetb=0v vcc=0v device ok 4 - 6 chapter 4. eprom lock bit write mode (1/2) resetb osc 12.5v ck1 ck2 ck3 k3 ~ k0 lock write ( 0100 ) 0000 vcc 6v 0v 1110 10 times repeat 12us x 10 = 120us 1 2 3 lock bit write 2us at 500khz ? ? ? 14.5clocks lock bit write mode (2/2) start ? reset (set lock bit write mode) wait cycle write cycle *1 count++ count=10? resetb=0v vcc=0v end count=0 yes no *1 repeat until near 100us. when 500khz osc1, repeat 10times (12us * 10 = 120us) 4 - 7 chapter 4. eprom lock bit read mode (1/2) lock bit read mode (2/2) osc1 12.5v lock read ( 0101 ) vcc 6v 0v lock bit output 1 2 2us at 500khz ? ? ? 14.5clocks start ? reset (set lock bit read mode) read lock bit (d5) resetb=0v vcc=0v end 4 - 8 chapter 4. eprom gms34004t/112t/140t (pin assignment & package) 16dip (standard ttl dip size) - width 300mil - pin to pin 100mil 20dip (standard ttl dip size) - width 300mil - pin to pin 100mil 20sop (standard ttl sop size) 24dip (skinny dip size) - width 300mil - pin to pin 100mil 24sop (standard sop size) 20 - 19 - 18 - 17 - 16 gnd 15 resetb 14 vdd 13 osc1 12 - 11 - k0 1 k1 2 k2 3 k3 4 d0 5 d1 6 d2 7 d3 8 d4 9 d5 10 resetb 1 gnd 2 - 3 - 4 - 5 - 6 k0 7 k1 8 k2 9 k3 10 d0 11 - 12 24 vdd 23 osc1 22 - 21 - 20 - 19 - 18 d5 17 d4 16 d3 15 d2 14 d1 13 - 16 vdd 15 osc1 14 - 13 - 12 d5 11 d4 10 d3 9 d2 resetb 1 gnd 2 k0 3 k1 4 k2 5 k3 6 d0 7 d1 8 4 - 9 chapter 4. eprom eprom(khz) mode eprom write only mode resetb osc 12.5v ck1 ck2 ck3 k3 ~ k0 pgm write ( 0110 ) ah d4 ~ d0 0000 vcc 6v 0v 1000 1110 al dh dl 10times repeat 12us x 10 = 120us 5times repeat eprom write next write 1000 0000 1110 ah al dh dl 2us at 500khz ? ? ? 14.5clocks 4 - 10 gms34004tm / 34112tm / 34140tm mode define device operation execute user pgm address in, data out item user mode eprom read mode eprom program mode 1byte pgm write 2byte pgm write program verify lock bit write lock bit read address in, data in address in, data in address in, data out lock bit write(set d5 to 1) lock bit out mode setting resetb = 0 ~ 3v vcc=3v vcc=6.0v vcc=6.0v k3~0=0010 k3~0=0110 k3~0=0111 - k3~0=0100 k3~0=0101 resetb =12.5v resetb =12.5v lock bit program mode resetb =12.5v vcc=6.0v, lock bit is d5. (default : unlock) chapter 4. eprom 4 - 11 port define nmos open drain i/o in eprom mode * undefined ports in this table are n.c (no connection) port name vdd resetb osc1 k0 k1 k2 k3 user mode 3.0v reset (0, 3.0v) clock input k0(input) k1(input) k2(input) k3(input) eprom mode 6.0v vpp (0, 12.5v) clock input read / write control address / data control d0 d1 d2 d3 d4 d5 d0(output) d1(output) d2(output) d3(output) d4(output) d5(output) a0 a5 da0 da4 lock bit output gnd 0v a1 a6 da1 da5 a2 a7 da2 da6 a3 a8 da3 da7 a4 a9 - - programming data device name gms34004tk rom size 512bytes blank data (hex) ff lock bit yes device address 0000 ~ 01ff file address 0000 ~ 01ff gms34112tk 1,024bytes ff yes 0000 ~ 03ff 0000 ~ 03ff GMS34140Tk 1,024bytes ff yes 0000 ~ 03ff 0000 ~ 03ff - if lock bit is set, the eprom of the device can not be read, because output is always ff. - input file : intel hexa format ( *.rhx ) chapter 4. eprom 4 - 12 write / read data conversion - you must change msb ~ lsb ? lsb ~ msb. - example hex binary (msb~lsb) 2c e4 8d 0010 1100 1110 0100 1000 1101 write read hex binary (msb~lsb) 34 27 b1 0011 0100 0010 0111 1011 0001 file / buffer data device (d3 ~ d0) checksum - it is calculated from the buffer of the programmer. - address range is the same as device address. - calculate mathod is the same as normal eprom devices (ex:27c128, 256 etc) programming control - osc1 & resetb control otp device, so you must count osc1 clocks in every state. - k ports control the internal state of the otp device(ex: read, write...). - d5~d0 ports are nmos open drain i/o in eprom mode. it must be pulled up by resistors (about 4.7~ 47k ohm). - the frequency rate of the osc1 clock is 10khz ~ 500khz. you can hold osc1 high or low state when you need. item range vcc 0 ~ 6.0v ?? 0.25v programming dc specification resetb 0 ~ 12.5v ?? 0.5v k-port d-port 0 ~ 0.2vcc(low) 0.8vcc ~ vcc (high) chapter 4. eprom 4 - 13 eprom read mode (1/2) eprom read mode (2/2) resetb osc1 12.5v for device verify or read. if you set lock bit, output data is all 'ff ? d4 ~ d0 k3 ~ k0 a9~a5 a4~a0 d3~d0 d7~d4 rom dump mode ( 0010 ) d5 port operation k port latch high bit instruction output low bit instruction output high bit address latch low bit address latch sense amp. operation vcc 6v 0v 12clock 8clock data strobe point 5clock data strobe point 5clock address setting data read repeat 1 2 3 start ? reset (set eprom read mode) address=first address set address read data address ++ resetb=0v vcc=0v end address > last address chapter 4. eprom 4 - 14 eprom write mode (1/4) eprom write mode (2/4) resetb osc1 12.5v k3 ~ k0 pgm write ( 0110 (1b)) a9~a5 a4~a0 d3~d0 d7~d4 d4 ~ d0 0000 1000 high bit instruction latch low bit instruction latch high bit address latch low bit address latch k port latch vcc 6v 0v 12clock 8clock 1 2 2 first address input first data input resetb osc1 k3 ~ k0 d4 ~ d0 1110 1110 12.5v 1101 verify vcc 6v eprom write time 3 3 4 chapter 4. eprom 4 - 15 eprom write mode (3/4) eprom write mode (4/4) resetb osc1 k3 ~ k0 d4 ~ d0 1101 12.5v d3~d0 d7~d4 verify a9~a5 a4~a0 d3~d0 d7~d4 0000 1000 high bit instruction latch low bit instruction latch high bit address latch low bit address latch high bit instruction output low bit instruction output next address input next data input vcc 6v data strobe point 5clock data strobe point 5clock 4 2 2 no fail yes pass no fail pass yes start ? reset (set eprom write mode) address=first address set address & data eprom write repeat until near 100us. when 4mhz osc1, repeat 10 times (12us*10=120us) resetb=0v vcc=0v end count=0 count ++ verify count=25? device fail address ++ eprom write (write one more time) address > last address eprom read mode verify all resetb=0v vcc=0v device ok chapter 4. eprom 4 - 16 lock bit write mode (1/3) lock bit write mode (2/3) osc1 resetb 12.5v k3 ~ k0 eprom mode lock write ( 0100 ) 0000 0000 k port latch vcc 6v 0v 12clock 8clock 1 2 2 osc1 1110 1100 12.5v write cycle repeat 2 times lock bit write resetb k3 ~ k0 vcc 6v repeat 10 times 4 3 chapter 4. eprom 4 - 17 lock bit write mode (3/3) start ? reset (set lock bit write mode) wait cycle write cycle *1 count++ count=10 resetb=0v vcc=0v end count=0 delay cycle (repeat 2 times) yes no *1 repeat until near 100us. when 4mhz osc1, repeat 10 times (12us * 10 = 120us) chapter 4. eprom 4 - 18 lock bit read mode (1/2) lock bit read mode (2/2) osc1 resetb 12.5v k3 ~ k0 lock read mode ( 0101 ) 1101 1101 k port latch d5 lock bit output vcc 6v 0v you can strobe at any time from here 12clock 8clock 1 2 3 start ? reset (set lock bit read mode) wait cycle read lock bit (d5) resetb=0v vcc=0v end chapter 4. eprom |
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